This invention relates to high-speed serial receiver circuitry and, more particularly, to handling the alignment of serial data streams received over multiple serial communication links.
Integrated circuits communicate with one another via communications pathways such as an input-output (I/O) buses. An increasingly important communications type is data communication in the form of serial data streams over serial communication links.
The implementation of recent serial transmission protocols, such as 100G Ethernet or Interlaken, typically involves the transmission of data in form of serial data streams over multiple serial communication links in parallel. Upon reception, the serial data streams are aggregated to implement a behavior equivalent to the transmission of the data over a single serial communication link. The aggregation of the serial data streams may involve the reception of synchronized serial data streams in a given order of serial communication links.
A situation may arise where a variation in the transmission delays between the multiple serial communication links causes the serial data streams to become misaligned. Some serial transmission protocols also allow serial communication links to become reordered during transmission. Thus, circuitry is required to perform processing steps to ensure alignment of received serial data streams. The processing steps include identification of word boundaries within each serial data stream, the alignment of all the serial data streams, and the arrangement of the serial communication links in a given order. Separate, independent state machine circuitry is typically assigned to each of the processing steps.